L3
L2
L1
affinity
hyperthreading
interprocessor
swappiness
cache
hectogon
disk cache
I/O bound
bank switching
repertoire
enregister
load-store architecture
uncache
superscalar
writethrough
writeback
primary storage
NOP sled
multiprocessing
tiling
RAM
random access memory
underrun
read/write memory
variable
random-access memory
random memory
cacheless
A20 gate
architecture
false sharing
overclock
read-through
program counter
silicon
virtual memory
memory cache
uniprocessor
paragraph
memory core
distributed computing
protected mode
DDR
shadow memory
miss
secondary storage
rebuffer
p-code
kernel space
subcache
expanded memory
branch register
buffer underrun
core
read-only memory chip
cacheability
x87
local memory
read-only memory
interchip
index register
bare-bones
mem
static random access memory
extended memory
recache
span
write-only memory
register
dynamic random access memory
transputer
data structure
superpipelining
virtual machine
underclock
access
microcircuit
integrated circuit
sequencer
scratchpad
spray
information engine
MIPS
core dump
microinstruction
Harvard architecture
flush
semaphore
warm
flash memory
million instructions per second
microarchitecture

English words for 'The third-level cache of a processor, farther away from the processor than the second-level cache.'

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