L3
L2
L1
affinity
hyperthreading
interprocessor
swappiness
cache
disk cache
hectogon
enregister
bank switching
repertoire
I/O bound
load-store architecture
superscalar
uncache
writethrough
primary storage
NOP sled
writeback
tiling
multiprocessing
variable
A20 gate
random memory
RAM
read/write memory
random access memory
random-access memory
underrun
cacheless
false sharing
architecture
read-through
overclock
program counter
silicon
uniprocessor
memory cache
virtual memory
memory core
distributed computing
paragraph
miss
DDR
shadow memory
protected mode
secondary storage
p-code
expanded memory
subcache
kernel space
rebuffer
cacheability
buffer underrun
branch register
x87
read-only memory chip
core
interchip
local memory
read-only memory
static random access memory
mem
index register
bare-bones
write-only memory
data structure
transputer
register
extended memory
recache
virtual machine
span
dynamic random access memory
superpipelining
integrated circuit
information engine
access
sequencer
scratchpad
spray
underclock
microcircuit
core dump
semaphore
Harvard architecture
million instructions per second
flash memory
flush
MIPS
warm
microinstruction
microarchitecture

English words for 'The third-level cache of a processor, farther away from the processor than the second-level cache.'

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