L1
L2
L3
primary storage
interprocessor
repertoire
enregister
hyperthreading
affinity
load-store architecture
A20 gate
I/O bound
program counter
hectogon
writethrough
cache
multiprocessing
random-access memory
random memory
RAM
overclock
random access memory
read/write memory
architecture
core
index register
paragraph
bank switching
local memory
writeback
swappiness
branch register
secondary storage
underrun
disk cache
subcache
uniprocessor
shadow memory
superscalar
tiling
instruction
neural net
cacheless
nanoprocessor
neural network
flop
Pent
virtual machine
multicache
x86
read-through
flush
NOP sled
kernel space
scratchpad
variable
bare-bones
underclock
hypercube
virtual memory
protected mode
dynamic random access memory
memory cache
superpipelining
northbridge
register
expanded memory
busy loop
static random access memory
nanoinstruction
false sharing
silicon
pipeline
flip-flop
cacheability
DDR
Pournelle's law
subprocessor
transputer
uncache
MIPS
core dump
interchip
Kermit
mass storage
storage device
load up
state
handshaking
million instructions per second
stored program
speedup
read-only memory chip
double precision

English words for 'The first-level cache of a processor, closer to the processor than the second-level cache.'

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