L1
L2
L3
primary storage
interprocessor
enregister
hyperthreading
repertoire
affinity
load-store architecture
program counter
hectogon
A20 gate
I/O bound
writethrough
multiprocessing
cache
read/write memory
overclock
RAM
random access memory
random-access memory
random memory
architecture
core
index register
swappiness
bank switching
local memory
writeback
paragraph
branch register
secondary storage
disk cache
subcache
underrun
shadow memory
uniprocessor
tiling
superscalar
nanoprocessor
instruction
neural net
neural network
cacheless
flop
Pent
virtual machine
flush
scratchpad
hypercube
kernel space
underclock
variable
bare-bones
read-through
multicache
x86
NOP sled
register
superpipelining
northbridge
memory cache
virtual memory
protected mode
dynamic random access memory
static random access memory
expanded memory
busy loop
DDR
silicon
false sharing
subprocessor
transputer
pipeline
nanoinstruction
cacheability
flip-flop
MIPS
Pournelle's law
uncache
core dump
interchip
Kermit
mass storage
stored program
million instructions per second
read-only memory chip
speedup
storage device
state
load up
handshaking
double precision

English words for 'The first-level cache of a processor, closer to the processor than the second-level cache.'

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