x87
x86-64
3DNow!
load-store architecture
protected mode
x86
instruction
branch register
superscalar
x86-32
program counter
repertoire
real mode
x86-16
i386
x64
stack machine
IA-32
AMD64
firmware
IA-64
local memory
programmable logic array
time-slicing
architecture
kernel space
stack
cache
memory cache
transputer
memory card
static memory allocation
flash memory
half adder
sequential logic
Mactel
multiprocessing
nanoinstruction
computer processor
lane
expanded memory
microprocessor
hectogon
memory
RAM-like
memistor
storage device
random access memory
buddy memory allocation
RAM
random memory
interprocessor
modified Harvard architecture
static random access memory
read/write memory
parallel port
enregister
random-access memory
hypercube
memory barrier
cryptoprocessor
coprocessor
span
full adder
parallelism
dead-bug
return-oriented programming
complex instruction set computing
double precision
read-only memory
dial in
complex instruction set computer
input device
Wallace tree
accelerator
CISC
data input device
information engine
underclock
NOP sled
long mode
combinational logic
PROM
userspace
Harvard architecture
operating system
bucket rendering
free list
number cruncher
virtual memory
RAM pack
memory cell
neural net
neural network
shadowing
high surrogate

English words for 'An extension to the x86 CPU instruction set architecture, providing direct hardware support for advanced floating-point arithmetic operations (rather than requiring them to be emulated in software).'

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